Level Shifted Discontinuous PWM Algorithms to Minimize Common Mode Voltage for Cascaded Multilevel Inverter Fed Induction Motor Drive

This paper presents combinations of level shifted pulse-width modulation algorithm with conventional discontinuous pulse-width modulation methods for cascaded multilevel inverters. In the proposed DPWM a zero sequence signal is injected in sinusoidal reference signal to generate various modulators w...

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Autors principals: Nayeemuddin, M. (Autor), Reddy, T. Bramhananda (Autor), Kumar, M. Vijaya (Autor)
Altres autors: G. Pulla Reddy Engineering College (Col·laborador)
Format: EJournal Article
Publicat: Institute of Advanced Engineering and Science, 2018-06-01.
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