3D Double Gate FinFET Construction of 30 nm Technology Node Impact Towards Short Channel Effect
This paper presents an investigation on properties of Double Gate FinFET (DGFinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, where depletion-layer widths of the source-drain corresponds to the channel length aside from constant fin height (HF...
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| Main Authors: | , , , , , , , , |
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| Format: | EJournal Article |
| Published: |
Institute of Advanced Engineering and Science,
2018-12-01.
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| Online Access: | Get fulltext |
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| LEADER | 02740 am a22003853u 4500 | ||
|---|---|---|---|
| 001 | ijeecs15268_10130 | ||
| 042 | |a dc | ||
| 100 | 1 | 0 | |a F. Roslan, Ameer |e author |
| 100 | 1 | 0 | |e contributor |
| 700 | 1 | 0 | |a Salehuddin, F. |e author |
| 700 | 1 | 0 | |a M.Zain, A.S. |e author |
| 700 | 1 | 0 | |a Kaharudin, K.E. |e author |
| 700 | 1 | 0 | |a Hazura, H. |e author |
| 700 | 1 | 0 | |a Hanim, A.R |e author |
| 700 | 1 | 0 | |a Idris, S. K |e author |
| 700 | 1 | 0 | |a Zarina, B.Z. |e author |
| 700 | 1 | 0 | |a Maheran A.H, Afifah |e author |
| 245 | 0 | 0 | |a 3D Double Gate FinFET Construction of 30 nm Technology Node Impact Towards Short Channel Effect |
| 260 | |b Institute of Advanced Engineering and Science, |c 2018-12-01. | ||
| 500 | |a https://ijeecs.iaescore.com/index.php/IJEECS/article/view/15268 | ||
| 520 | |a This paper presents an investigation on properties of Double Gate FinFET (DGFinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, where depletion-layer widths of the source-drain corresponds to the channel length aside from constant fin height (HFIN) and the fin thickness (TFIN). Virtual fabrication process of 3-dimensional (3D) design is applied throughout the study and its electrical characterization is employed and substantial is shown towards the FinFET design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio) at 563138.35 compared to prediction made by the International Technology Roadmap Semiconductor (ITRS) 2013. Conclusively, the incremental in ratio has fulfilled the desired in incremental on the drive current as well as reductions of the leakage current. Threshold voltage (VTH) meanwhile has also achieved the nominal requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.676±12.7% V. The ION , IOFF and VTH obtained from the device has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology. | ||
| 540 | |a Copyright (c) 2018 Institute of Advanced Engineering and Science | ||
| 540 | |a http://creativecommons.org/licenses/by-nc/4.0 | ||
| 546 | |a eng | ||
| 690 | |||
| 690 | |a MOSFET; Multi Gate; Double-Gate FinFET; Short Channel Effects. | ||
| 655 | 7 | |a info:eu-repo/semantics/article |2 local | |
| 655 | 7 | |a info:eu-repo/semantics/publishedVersion |2 local | |
| 655 | 7 | |2 local | |
| 786 | 0 | |n Indonesian Journal of Electrical Engineering and Computer Science; Vol 12, No 3: December 2018; 1358-1365 | |
| 786 | 0 | |n 2502-4760 | |
| 786 | 0 | |n 2502-4752 | |
| 786 | 0 | |n 10.11591/ijeecs.v12.i3 | |
| 787 | 0 | |n https://ijeecs.iaescore.com/index.php/IJEECS/article/view/15268/10130 | |
| 856 | 4 | 1 | |u https://ijeecs.iaescore.com/index.php/IJEECS/article/view/15268/10130 |z Get fulltext |