Implementation of a camera system using nios II on the altera DE2-70 board
The implementation of a camera system with a field programmable gate array (FPGA) is an important step within research towards constructing a video processing architecture design based on FPGA. This paper presents the design and implementation of a camera system using the Nios II soft-core embedded...
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| Format: | EJournal Article |
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Institute of Advanced Engineering and Science,
2019-05-01.
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| Online Access: | Get fulltext |
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| LEADER | 02319 am a22003013u 4500 | ||
|---|---|---|---|
| 001 | ijeecs16697_11911 | ||
| 042 | |a dc | ||
| 100 | 1 | 0 | |a Cheng, Chan Boon |e author |
| 100 | 1 | 0 | |e contributor |
| 700 | 1 | 0 | |a Jambek, Asral Bahari |e author |
| 245 | 0 | 0 | |a Implementation of a camera system using nios II on the altera DE2-70 board |
| 260 | |b Institute of Advanced Engineering and Science, |c 2019-05-01. | ||
| 500 | |a https://ijeecs.iaescore.com/index.php/IJEECS/article/view/16697 | ||
| 520 | |a The implementation of a camera system with a field programmable gate array (FPGA) is an important step within research towards constructing a video processing architecture design based on FPGA. This paper presents the design and implementation of a camera system using the Nios II soft-core embedded processor from Altera. The proposed camera system is a flexible platform for the implementation of other systems such as image processing and video processing. The system architecture is designed using the Quartus II SOPC Builder System and implemented on an Altera DE2-70 development platform. The image or video is captured using a Terasic TRDB-D5M camera and stored into two different synchronous dynamic random access memories (SDRAM) using an SDRAM Controller. The specifications of the Terasic TRDB-D5M and SDRAM are examined to confirm that the recorded and stored data match. The results of this experiment show that the system is able to record and store data correctly into SDRAM. The data in the SDRAM correctly displays the recorded image on a VGA monitor. | ||
| 540 | |a Copyright (c) 2018 Institute of Advanced Engineering and Science | ||
| 540 | |a http://creativecommons.org/licenses/by-nc/4.0 | ||
| 546 | |a eng | ||
| 690 | |||
| 690 | |a Terasic TRDB-D5M, SOPC Builder, SDRAM Controller, Cyclon II EP2C70 FPGA | ||
| 655 | 7 | |a info:eu-repo/semantics/article |2 local | |
| 655 | 7 | |a info:eu-repo/semantics/publishedVersion |2 local | |
| 655 | 7 | |2 local | |
| 786 | 0 | |n Indonesian Journal of Electrical Engineering and Computer Science; Vol 14, No 2: May 2019; 513-522 | |
| 786 | 0 | |n 2502-4760 | |
| 786 | 0 | |n 2502-4752 | |
| 786 | 0 | |n 10.11591/ijeecs.v14.i2 | |
| 787 | 0 | |n https://ijeecs.iaescore.com/index.php/IJEECS/article/view/16697/11911 | |
| 856 | 4 | 1 | |u https://ijeecs.iaescore.com/index.php/IJEECS/article/view/16697/11911 |z Get fulltext |