Reversible logic in pipelined low power vedic multiplier
With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power V...
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| Format: | EJournal Article |
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Institute of Advanced Engineering and Science,
2019-12-01.
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| Online Access: | Get fulltext |
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| LEADER | 02514 am a22003013u 4500 | ||
|---|---|---|---|
| 001 | ijeecs17990_13160 | ||
| 042 | |a dc | ||
| 100 | 1 | 0 | |a Eshack, Ansiya |e author |
| 100 | 1 | 0 | |e contributor |
| 700 | 1 | 0 | |a Krishnakumar, S. |e author |
| 245 | 0 | 0 | |a Reversible logic in pipelined low power vedic multiplier |
| 260 | |b Institute of Advanced Engineering and Science, |c 2019-12-01. | ||
| 500 | |a https://ijeecs.iaescore.com/index.php/IJEECS/article/view/17990 | ||
| 520 | |a With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers. | ||
| 540 | |a Copyright (c) 2019 Institute of Advanced Engineering and Science | ||
| 540 | |a http://creativecommons.org/licenses/by-nc/4.0 | ||
| 546 | |a eng | ||
| 690 | |a Electronics; VLSI design; FPGA | ||
| 690 | |a Vedic multiplier, Reversible logic gate, FPGA, Pipelining, Toffoli gate, Low power | ||
| 655 | 7 | |a info:eu-repo/semantics/article |2 local | |
| 655 | 7 | |a info:eu-repo/semantics/publishedVersion |2 local | |
| 655 | 7 | |2 local | |
| 786 | 0 | |n Indonesian Journal of Electrical Engineering and Computer Science; Vol 16, No 3: December 2019; 1265-1272 | |
| 786 | 0 | |n 2502-4760 | |
| 786 | 0 | |n 2502-4752 | |
| 786 | 0 | |n 10.11591/ijeecs.v16.i3 | |
| 787 | 0 | |n https://ijeecs.iaescore.com/index.php/IJEECS/article/view/17990/13160 | |
| 856 | 4 | 1 | |u https://ijeecs.iaescore.com/index.php/IJEECS/article/view/17990/13160 |z Get fulltext |