Parallel multi-layer selector S-Box based on lorenz chaotic system with FPGA implementation
The substitution box (S-box) is the main block in the encryption system, which replaces the non-encrypted data by dynamic secure and hidden data. S-box can be designed based on complex nonlinear chaotic systems that presented in recent papers as a chaotic S-Box. The hardware implementation of these...
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Institute of Advanced Engineering and Science,
2020-08-01.
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LEADER | 02620 am a22003013u 4500 | ||
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001 | ijeecs20794_14001 | ||
042 | |a dc | ||
100 | 1 | 0 | |a Saber, Mohamed |e author |
100 | 1 | 0 | |e contributor |
700 | 1 | 0 | |a Hagras, Esam |e author |
245 | 0 | 0 | |a Parallel multi-layer selector S-Box based on lorenz chaotic system with FPGA implementation |
260 | |b Institute of Advanced Engineering and Science, |c 2020-08-01. | ||
500 | |a https://ijeecs.iaescore.com/index.php/IJEECS/article/view/20794 | ||
520 | |a The substitution box (S-box) is the main block in the encryption system, which replaces the non-encrypted data by dynamic secure and hidden data. S-box can be designed based on complex nonlinear chaotic systems that presented in recent papers as a chaotic S-Box. The hardware implementation of these chaotic systems suffers from long processing time (low speed), and high-power consumption since it requires a large number of non-linear computational models. In this paper, we present a high-speed FPGA implementation of parallel multi-layer selector substitution boxes based on the lorenz chaotic system (PMLS S-Box). The proposed PMLS chaotic S-box is modeled using xilinx system generator (XSG) in 32 bits fixed-point format, and the architecture implemented into Xilinx Spartan-6 X6SLX45 board. The maximum frequency of the proposed PMLS chaotic S-box is 381.764MHz, with dissipates of 77 mwatt. Compared to other S-box chaotic systems, the proposed one achieves a higher frequency and lower power consumption. In addition, the proposed PMLS chaotic S-box is analyzed based on S-box standard tests such as; Bijectivity property, nonlinearity, strict avalanche criterion, differential probability, and bits independent criterion. The five different standard results for the proposed S-box indicate that PMLSC can effectively resist crypto-analysis attacks, and is suitable for secure communications. | ||
540 | |a Copyright (c) 2020 Institute of Advanced Engineering and Science | ||
540 | |a http://creativecommons.org/licenses/by-nc/4.0 | ||
546 | |a eng | ||
690 | |||
690 | |a Chaotic systems; S-box; FPGA | ||
655 | 7 | |a info:eu-repo/semantics/article |2 local | |
655 | 7 | |a info:eu-repo/semantics/publishedVersion |2 local | |
655 | 7 | |2 local | |
786 | 0 | |n Indonesian Journal of Electrical Engineering and Computer Science; Vol 19, No 2: August 2020; 784-792 | |
786 | 0 | |n 2502-4760 | |
786 | 0 | |n 2502-4752 | |
786 | 0 | |n 10.11591/ijeecs.v19.i2 | |
787 | 0 | |n https://ijeecs.iaescore.com/index.php/IJEECS/article/view/20794/14001 | |
856 | 4 | 1 | |u https://ijeecs.iaescore.com/index.php/IJEECS/article/view/20794/14001 |z Get fulltext |