Adaptive random testing with total cartesian distance for black box circuit under test
Testing and verification of digital circuits is of vital importance in electronics industry. Moreover, key designs require preservation of their intellectual property that might restrict access to the internal structure of circuit under test. Random testing is a classical solution to black box testi...
Saved in:
| Main Authors: | , , , |
|---|---|
| Other Authors: | |
| Format: | EJournal Article |
| Published: |
Institute of Advanced Engineering and Science,
2020-11-01.
|
| Subjects: | |
| Online Access: | Get fulltext |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | Testing and verification of digital circuits is of vital importance in electronics industry. Moreover, key designs require preservation of their intellectual property that might restrict access to the internal structure of circuit under test. Random testing is a classical solution to black box testing as it generates test patterns without using the structural implementation of the circuit under test. However, random testing ignores the importance of previously applied test patterns while generating subsequent test patterns. An improvement to random testing is Antirandom that diversifies every subsequent test pattern in the test sequence. Whereas, computational intensive process of distance calculation restricts its scalability for large input circuit under test. Fixed sized candidate set adaptive random testing uses predetermined number of patterns for distance calculations to avoid computational complexity. A combination of max-min distance with previously executed patterns is carried out for each test pattern candidate. However, the reduction in computational complexity reduces the effectiveness of test set in terms of fault coverage. This paper uses a total cartesian distance based approach on fixed sized candidate set to enhance diversity in test sequence. The proposed approach has a two way effect on the test pattern generation as it lowers the computational intensity along with enhancement in the fault coverage. Fault simulation results on ISCAS'85 and ISCAS'89 benchmark circuits show that fault coverage of the proposed method increases up to 20.22% compared to previous method. |
|---|---|
| Item Description: | https://ijeecs.iaescore.com/index.php/IJEECS/article/view/21904 |