Design of very low-voltages and high-performance CMOS gate-driven operational amplifier
This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS...
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| Main Authors: | , , |
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| Format: | EJournal Article |
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Institute of Advanced Engineering and Science,
2020-11-01.
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| Online Access: | Get fulltext |
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| LEADER | 02585 am a22003133u 4500 | ||
|---|---|---|---|
| 001 | ijeecs22293_14264 | ||
| 042 | |a dc | ||
| 100 | 1 | 0 | |a AL-Qaysi, Hayder Khaleel |e author |
| 100 | 1 | 0 | |e contributor |
| 700 | 1 | 0 | |a Mohammed Jasim, Musaab |e author |
| 700 | 1 | 0 | |a Manhal Hameed, Siraj |e author |
| 245 | 0 | 0 | |a Design of very low-voltages and high-performance CMOS gate-driven operational amplifier |
| 260 | |b Institute of Advanced Engineering and Science, |c 2020-11-01. | ||
| 500 | |a https://ijeecs.iaescore.com/index.php/IJEECS/article/view/22293 | ||
| 520 | |a This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94 at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies' voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits. | ||
| 540 | |a Copyright (c) 2020 Institute of Advanced Engineering and Science | ||
| 540 | |a http://creativecommons.org/licenses/by-nc/4.0 | ||
| 546 | |a eng | ||
| 690 | |||
| 690 | |a Analog MOSFETs circuits; CMOS operational amplifier; Folded cascode technique; Gate-driven; LV power supply | ||
| 655 | 7 | |a info:eu-repo/semantics/article |2 local | |
| 655 | 7 | |a info:eu-repo/semantics/publishedVersion |2 local | |
| 655 | 7 | |2 local | |
| 786 | 0 | |n Indonesian Journal of Electrical Engineering and Computer Science; Vol 20, No 2: November 2020; 670-679 | |
| 786 | 0 | |n 2502-4760 | |
| 786 | 0 | |n 2502-4752 | |
| 786 | 0 | |n 10.11591/ijeecs.v20.i2 | |
| 787 | 0 | |n https://ijeecs.iaescore.com/index.php/IJEECS/article/view/22293/14264 | |
| 856 | 4 | 1 | |u https://ijeecs.iaescore.com/index.php/IJEECS/article/view/22293/14264 |z Get fulltext |