Improving bit error-rate based on adaptive Bose-Chaudhuri Hocquenghem concatenated with convolutional codes
Several algorithms have been proposed to avoid the error floor region, such as the concatenation codes that requires high computational demands in addition to high complexity. This paper proposes a technique based on using cascaded BCH and convolutional codes that leads to better error correction pe...
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| Main Authors: | , , |
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| Format: | EJournal Article |
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Institute of Advanced Engineering and Science,
2021-08-01.
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| LEADER | 02521 am a22003133u 4500 | ||
|---|---|---|---|
| 001 | ijeecs24596_15340 | ||
| 042 | |a dc | ||
| 100 | 1 | 0 | |a Samy, Ahmed |e author |
| 100 | 1 | 0 | |e contributor |
| 700 | 1 | 0 | |a Hassan, Ashraf Y. |e author |
| 700 | 1 | 0 | |a Zakaria, Hatem M. |e author |
| 245 | 0 | 0 | |a Improving bit error-rate based on adaptive Bose-Chaudhuri Hocquenghem concatenated with convolutional codes |
| 260 | |b Institute of Advanced Engineering and Science, |c 2021-08-01. | ||
| 500 | |a https://ijeecs.iaescore.com/index.php/IJEECS/article/view/24596 | ||
| 520 | |a Several algorithms have been proposed to avoid the error floor region, such as the concatenation codes that requires high computational demands in addition to high complexity. This paper proposes a technique based on using cascaded BCH and convolutional codes that leads to better error correction performance. Moreover, an adaptive method based on sensing the channel's noise to determine the number of the parity bits that will be added to the used BCH that reduces the consumed bandwidth and the transmitted parity bits is presented. A further enhancement is fulfilled by using parallel processing branches, resulting in reducing the consumed time and speed up the performance. The results show that the proposed code presents a better performance. A high reduction in the number of cycles that will be used in the encoding and decoding compared with the classical method and finally a flexible parity bits method based on the signal-to-noise ratio of the channel that reduced the parity bits which leads to reduce the consumed bandwidth. The MATLAB simulation and the field programmable gate array (FPGA) implementation will be provided in this paper to validate the proposed concept. | ||
| 540 | |a Copyright (c) 2021 Institute of Advanced Engineering and Science | ||
| 540 | |a http://creativecommons.org/licenses/by-nc/4.0 | ||
| 546 | |a eng | ||
| 690 | |||
| 690 | |a Bose-Chaudhuri Hocquenghem; Concatenation; Convolutional; Decoder; Encoder; Viterbi | ||
| 655 | 7 | |a info:eu-repo/semantics/article |2 local | |
| 655 | 7 | |a info:eu-repo/semantics/publishedVersion |2 local | |
| 655 | 7 | |2 local | |
| 786 | 0 | |n Indonesian Journal of Electrical Engineering and Computer Science; Vol 23, No 2: August 2021; 890-901 | |
| 786 | 0 | |n 2502-4760 | |
| 786 | 0 | |n 2502-4752 | |
| 786 | 0 | |n 10.11591/ijeecs.v23.i2 | |
| 787 | 0 | |n https://ijeecs.iaescore.com/index.php/IJEECS/article/view/24596/15340 | |
| 856 | 4 | 1 | |u https://ijeecs.iaescore.com/index.php/IJEECS/article/view/24596/15340 |z Get fulltext |