A Long-wire-connected and Multi-channel 3D Network-on-chip Design for Many-core System
To reduce traffic jam caused by various data competitions for channel, we present a low delay and energy efficient network-on-chip with three channels for different type's data. Hence, the transmission for control data between cores won't be congested by the big amount of data transmitted...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | EJournal Article |
| Published: |
Institute of Advanced Engineering and Science,
2013-12-01.
|
| Subjects: | |
| Online Access: | Get fulltext |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| LEADER | 02285 am a22003133u 4500 | ||
|---|---|---|---|
| 001 | ijeecs2877_4005 | ||
| 042 | |a dc | ||
| 100 | 1 | 0 | |a Hai, Tan |e author |
| 100 | 1 | 0 | |e contributor |
| 700 | 1 | 0 | |a Talpur, Shahnawaz |e author |
| 700 | 1 | 0 | |a Soomro, Amir Mahmood |e author |
| 700 | 1 | 0 | |a Mao, Chen Hong |e author |
| 245 | 0 | 0 | |a A Long-wire-connected and Multi-channel 3D Network-on-chip Design for Many-core System |
| 260 | |b Institute of Advanced Engineering and Science, |c 2013-12-01. | ||
| 520 | |a To reduce traffic jam caused by various data competitions for channel, we present a low delay and energy efficient network-on-chip with three channels for different type's data. Hence, the transmission for control data between cores won't be congested by the big amount of data transmitted from caches to core, and it achieves better performance in latency and energy. Our strategy is to make a directive long wire to connect two nodes in the same row or column, and distribute these connective wires to different layers which are connected by 3D stacking technology. In the many-core system applied with this topology, every pair of core-cache nodes are at most 5 hops away while real-time and short control information is transmitted by a 2D mesh network. The experimental results show up to 23% of network latency reduction and up to 15% energy reduction when compared to a 3D network-on-chip. DOI: http://dx.doi.org/10.11591/telkomnika.v11i12.2764 | ||
| 540 | |a Copyright (c) 2013 Institute of Advanced Engineering and Science | ||
| 540 | |a http://creativecommons.org/licenses/by-nc-nd/4.0 | ||
| 546 | |a eng | ||
| 690 | |a Technology; Electrical, Electronics and Computer Engineering;NOC Architecture | ||
| 690 | |a multi-channel; many-core system; 3D stack; long-wire-connected | ||
| 655 | 7 | |a info:eu-repo/semantics/article |2 local | |
| 655 | 7 | |a info:eu-repo/semantics/publishedVersion |2 local | |
| 655 | 7 | |2 local | |
| 786 | 0 | |n Indonesian Journal of Electrical Engineering and Computer Science; Vol 11, No 12: December 2013; 7081-7087 | |
| 786 | 0 | |n 2502-4760 | |
| 786 | 0 | |n 2502-4752 | |
| 786 | 0 | |n 10.11591/ijeecs.v11.i12 | |
| 787 | 0 | |n https://ijeecs.iaescore.com/index.php/IJEECS/article/view/2877/4005 | |
| 856 | 4 | 1 | |u https://ijeecs.iaescore.com/index.php/IJEECS/article/view/2877/4005 |z Get fulltext |