Architecture of ASIP Crypto-Processor for Dynamic Runtime Security Applications
Nowadays, demands of data security are increasing, especially after introduction of wireless communications to the masses. Cryptographic algorithms are mainly used to obtain confidentiality and integrity of data in communication. There are a variety of encryption algorithms have been developed. This...
Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | EJournal Article |
| Published: |
Institute of Advanced Engineering and Science,
2016-11-01.
|
| Subjects: | |
| Online Access: | Get fulltext |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| LEADER | 02472 am a22002893u 4500 | ||
|---|---|---|---|
| 001 | ijeecs5982_5317 | ||
| 042 | |a dc | ||
| 100 | 1 | 0 | |a Saad, Mahaba |e author |
| 700 | 1 | 0 | |a Youssef, Khalid |e author |
| 700 | 1 | 0 | |a Tarek, Mohamed |e author |
| 700 | 1 | 0 | |a Abdel-Kader, Hala |e author |
| 245 | 0 | 0 | |a Architecture of ASIP Crypto-Processor for Dynamic Runtime Security Applications |
| 260 | |b Institute of Advanced Engineering and Science, |c 2016-11-01. | ||
| 500 | |a https://ijeecs.iaescore.com/index.php/IJEECS/article/view/5982 | ||
| 520 | |a Nowadays, demands of data security are increasing, especially after introduction of wireless communications to the masses. Cryptographic algorithms are mainly used to obtain confidentiality and integrity of data in communication. There are a variety of encryption algorithms have been developed. This paper provides quantitative analysis and comparison of some symmetric key cryptographic ciphers (DES, 3DES, AES, Blowfish, RC5, and RC6). The quantitative analysis approach is a step towards optimizing the security operations for an efficient next generation family of network processors with enhanced speed and power performance. A framework will be proposed as a reference model for quantitative analysis of security algorithm mathematical and logical operations. This paper also provides a dynamic crypto processor used for selected symmetric key cryptographic ciphers and provides an implementation of 16bit cryptographic processor that performs logical operations and arithmetic operations like rotate shift left, modular addition 2^16, S_box operation, and key expansion operation on spartan6 lower power, xc6slx150L-1lfgg676 FPGA. Simulation results show that developed processor working with high Speed, low power, and low delay time. | ||
| 540 | |a Copyright (c) 2016 Indonesian Journal of Electrical Engineering and Computer Science | ||
| 540 | |a http://creativecommons.org/licenses/by-nc-nd/4.0 | ||
| 546 | |a eng | ||
| 655 | 7 | |a info:eu-repo/semantics/article |2 local | |
| 655 | 7 | |a info:eu-repo/semantics/publishedVersion |2 local | |
| 655 | 7 | |2 local | |
| 786 | 0 | |n Indonesian Journal of Electrical Engineering and Computer Science; Vol 4, No 2: November 2016; 412-423 | |
| 786 | 0 | |n 2502-4760 | |
| 786 | 0 | |n 2502-4752 | |
| 786 | 0 | |n 10.11591/ijeecs.v4.i2 | |
| 787 | 0 | |n https://ijeecs.iaescore.com/index.php/IJEECS/article/view/5982/5317 | |
| 856 | 4 | 1 | |u https://ijeecs.iaescore.com/index.php/IJEECS/article/view/5982/5317 |z Get fulltext |