Customized Hardware Crypto Engine for Wireless Sensor Networks
Nowadays, managing for optimal security to wireless sensor networks (WSNs) has emerged as an active research area. The challenging topics in this active research involve various issues such as energy consumption, routing algorithms, selection of sensors location according to a given premise, robustn...
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| Main Authors: | , , , |
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| Format: | EJournal Article |
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Institute of Advanced Engineering and Science,
2017-07-01.
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| Subjects: | |
| Online Access: | Get fulltext |
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| LEADER | 02517 am a22003253u 4500 | ||
|---|---|---|---|
| 001 | ijeecs7308_6992 | ||
| 042 | |a dc | ||
| 100 | 1 | 0 | |a Awadalla, Medhat |e author |
| 100 | 1 | 0 | |e contributor |
| 700 | 1 | 0 | |a Al Maashri, Ahmed |e author |
| 700 | 1 | 0 | |a Pathuri, Lavanya |e author |
| 700 | 1 | 0 | |a Ahmad, Afaq |e author |
| 245 | 0 | 0 | |a Customized Hardware Crypto Engine for Wireless Sensor Networks |
| 260 | |b Institute of Advanced Engineering and Science, |c 2017-07-01. | ||
| 500 | |a https://ijeecs.iaescore.com/index.php/IJEECS/article/view/7308 | ||
| 520 | |a Nowadays, managing for optimal security to wireless sensor networks (WSNs) has emerged as an active research area. The challenging topics in this active research involve various issues such as energy consumption, routing algorithms, selection of sensors location according to a given premise, robustness, and efficiency. Despite the open problems in WSNs, already a high number of applications available shows the activeness of emerging research in this area. Through this paper, authors propose an alternative routing algorithmic approach that accelerate the existing algorithms in sense to develop a power-efficient crypto system to provide the desired level of security on a smaller footprint, while maintaining real-time performance and mapping them to customized hardware. To achieve this goal, the algorithms have been first analyzed and then profiled to recognize their computational structure that is to be mapped into hardware accelerators in platform of reconfigurable computing devices. An intensive set of experiments have been conducted and the obtained results show that the performance of the proposed architecture based on algorithms implementation outperforms the software implementation running on contemporary CPU in terms of the power consumption and throughput. | ||
| 540 | |a Copyright (c) 2017 Institute of Advanced Engineering and Science | ||
| 540 | |a http://creativecommons.org/licenses/by-nc-nd/4.0 | ||
| 546 | |a eng | ||
| 690 | |||
| 690 | |||
| 655 | 7 | |a info:eu-repo/semantics/article |2 local | |
| 655 | 7 | |a info:eu-repo/semantics/publishedVersion |2 local | |
| 655 | 7 | |2 local | |
| 786 | 0 | |n Indonesian Journal of Electrical Engineering and Computer Science; Vol 7, No 1: July 2017; 263-275 | |
| 786 | 0 | |n 2502-4760 | |
| 786 | 0 | |n 2502-4752 | |
| 786 | 0 | |n 10.11591/ijeecs.v7.i1 | |
| 787 | 0 | |n https://ijeecs.iaescore.com/index.php/IJEECS/article/view/7308/6992 | |
| 856 | 4 | 1 | |u https://ijeecs.iaescore.com/index.php/IJEECS/article/view/7308/6992 |z Get fulltext |