Reversible logic in pipelined low power vedic multiplier

by Eshack, Ansiya, Krishnakumar, S.
Published 2019

Pipeline architectures of Three-dimensional daubechies wavelet transform using hybrid method

by Huda Ja'afar, Noor, Ahmad, Afandi
Published 2019

Low power design of ultra wideband PLL using 90 nm CMOS technology

by Noor Al Amin, Fadhilah Binti, Ahmad, Nabihah, Ruslan, Siti Hawa
Published 2020

Advances on Low Power Designs for SRAM Cell

by Rahman, Labonnah Farzana, F. B. Amir, Mohammad, Bin Ibne Reaz, Mamun, Marufuzzaman, Mohd, Husain, Hafizah
Published 2014

Obstacle aware delay optimized rectilinear steiner minimum tree routing

by G, Shyamala, Prasad, G R
Published 2019

Power optimization of binary division based on FPGA

by Nasser, Fadi T., Hashim, Ivan A.
Published 2021