Implementasi Sistem Penghilang Derau Adaptif Menggunakan Algoritma LMS pada FPGA Altera Flex10KLC84
The Adaptive Noise Cancelling Systemhas been implemented in FPGA's AlteraFelx10KCL84, chip which has 576 LE and 3 EAB. Thesystem has data communication capability betweenPC and system and the baudrate is 9,600bps. Dataformat using 8-bit data width two's complementinteger and 8 scale factor...
Uloženo v:
Hlavní autoři: | , |
---|---|
Médium: | EJournal Article |
Vydáno: |
IndoCEISS in colaboration with Universitas Gadjah Mada, Indonesia.,
2013-05-30.
|
Témata: | |
On-line přístup: | Get Fulltext |
Tagy: |
Přidat tag
Žádné tagy, Buďte první, kdo otaguje tento záznam!
|
Internet
Get Fulltext3rd Floor Main Library
Signatura: |
A1234.567 |
---|---|
Jednotka 1 | Dostupné |