Timing violation reduction in the FPGA prototyped design using failed path fixes and time borrowing techniques
A fascinating property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as it can borrow time from the shorter paths in the subsequent logic states. Time borrowing technique is a common method used to satisfy timing violation in an FPGA protot...
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| Main Authors: | , , , |
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| Format: | EJournal Article |
| Published: |
Institute of Advanced Engineering and Science,
2019-05-01.
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| Subjects: | |
| Online Access: | Get fulltext |
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Get fulltext3rd Floor Main Library
| Call Number: |
A1234.567 |
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| Copy 1 | Available |