Low power design of ultra wideband PLL using 90 nm CMOS technology
The rapid growth of the electronic system has become one of the challenges in the high performance of very large scale integration (VLSI) design and has contributed to the evolution of phase locked loop (PLL) system design as one of the inevitable and significant necessities in the modern days. This...
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| Main Authors: | , , |
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| Format: | EJournal Article |
| Published: |
Institute of Advanced Engineering and Science,
2020-11-01.
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| Subjects: | |
| Online Access: | Get fulltext |
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Get fulltext3rd Floor Main Library
| Call Number: |
A1234.567 |
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| Copy 1 | Available |