Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters
In various VLSI based digital systems, on-chip interconnects have become the system bottleneck in state-of-the-art chips, limiting the performance of high-speed clock distributions and data communication devices in terms of propagation delay and power consumption. Increasing power requirements and p...
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| Autors principals: | , |
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| Format: | EJournal Article |
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Institute of Advanced Engineering and Science,
2018-04-01.
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| Accés en línia: | Get fulltext |
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