Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters
In various VLSI based digital systems, on-chip interconnects have become the system bottleneck in state-of-the-art chips, limiting the performance of high-speed clock distributions and data communication devices in terms of propagation delay and power consumption. Increasing power requirements and p...
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| Autores principales: | , |
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| Formato: | EJournal Article |
| Publicado: |
Institute of Advanced Engineering and Science,
2018-04-01.
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| Acceso en línea: | Get fulltext |
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| Número de Clasificación: |
A1234.567 |
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| Copia 1 | Disponible |