A Comprehensive Review on Applications of Don't Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems
Massive power consumption during VLSI testing is a serious threat to reliability concerns of ubiquitous silicon industry. A significant amount of low-power methodologies are proposed in the relevant literature to address this issue of test mode power consumption and don't care bit(X) filling ap...
שמור ב:
| Main Authors: | , |
|---|---|
| מחברים אחרים: | |
| פורמט: | EJournal Article |
| יצא לאור: |
Institute of Advanced Engineering and Science,
2018-12-01.
|
| נושאים: | |
| גישה מקוונת: | Get fulltext |
| תגים: |
הוספת תג
אין תגיות, היה/י הראשונ/ה לתייג את הרשומה!
|
אינטרנט
Get fulltext3rd Floor Main Library
| סימן המיקום: |
A1234.567 |
|---|---|
| עותק 1 | זמין |