A Comprehensive Review on Applications of Don't Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems
Massive power consumption during VLSI testing is a serious threat to reliability concerns of ubiquitous silicon industry. A significant amount of low-power methodologies are proposed in the relevant literature to address this issue of test mode power consumption and don't care bit(X) filling ap...
Saved in:
| Main Authors: | , |
|---|---|
| 其他作者: | |
| 格式: | EJournal Article |
| 出版: |
Institute of Advanced Engineering and Science,
2018-12-01.
|
| 主題: | |
| 在線閱讀: | Get fulltext |
| 標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|